~~NOTOC~~
======  Minute of meeting on 2018.01.24 ======


===== 1.  Attendees  =====
-- Alexander Pawlitzki (Thales-Alenia Space, Germany) \\
-- Anthony Le (Boeing) \\
-- Austin Lesea (Xilinx) \\
-- Barrie Timpe (Xilinx FAE) \\
-- Dan Elftmann (Xilinx) \\
-- David Lee (Sandia Labs) \\
-- Eliot Glaser (Northrop Grumman) \\
-- Gary Swift (meeting moderator, Swift ERS) \\
-- Joseph (Joe) Marshall (BAE) \\
-- Kevin Wray (Boeing) \\
-- Luis Berrojo (TAS-E, Thales-Alenia Space, España) \\
-- Mike Wirthlin (BYU) \\
-- Philip Chang (RUAG)\\
-- Pierre Maillard (Xilinx) \\
-- Ron Smith (Northrop Grumman) \\
-- Scott Arlo Anderson (SEAKR) \\
-- Sebastian Garcia (Slabs) \\
-- Stephen Thomas (Boeing) \\
-- TAS-E (Thales-Alenia Space, España) team (Diana, Filip, Luis)\\
-- Victor Liau (Hughes Network Systems) \\


===== 2.  Topics covered =====

//NOTE: The following are very brief descriptions. Being this a Wiki, please complete/expand/correct them if you think we are missing interesting information (especially regarding anything important for future reference). 
//

Paragraphs below are comments made by Gary (unless otherwise indicated).

**Kintex UltraScale KU060**. David comments he obtained funding from Sandia for beam test. Maybe 16 to 24 beam hours and also development engineering hours. Priorities: latchup/microlatchup test. Maybe just in air, using a heat gun. 

BAE has interest in **more V-7 testing**. Joe confirms this, but can't speak about it at this point. 

Regarding the **ZUS+ latchup suppression experiment**, Heather is looking for donated time on LANL's 14 MeV irradiation facility.
We will need to make our own tests to check the parts after irradiation, instead of not using Xilinx' resources for production and characterization tests. 
For a test board, the default candidate is the ZCU102. Will need to rework, putting the neutron irradiated parts, add heating, and use onboard's temperature monitoring capability. We are needing beam hours for this test. 
Probably David can obtain funding for this.

**JCM Configmon with SelectMap** development status. Mike comments that his group is making progress. Would be useful to use the fault-injection capability to flush-out any possible JCM issues. Currently they need an UltraScale to test the 32-bit S-Map I/F.

**Gen-4 infrastructure development** milestone: Complete motherboard connections spreadsheet sent to STS, they're working on schematics and layout. Next task: KU060 DUT card. There's also a small adapter board required between and FMC connector and 3x 40-pin IDE connectors for the FuncMon ribbon cables.

Dan: Xilinx is still collecting requirements for the **space applications targetted UltraScale-based board**. The idea is to enable prototyping CRAM scrubbing techniques, that can also put on to the XRTC infrastructure and,  maybe, beam testing. There's a decision pending on using a dedicated connector for the SelectMap, and possibly other configuration-related I/Os. David suggests to look at what was implemented when testing V-5.
For configuration memory, FRAM and MRAM options are considered and specific parts need to be defined.


Dan mentions the V-5QV overview document has been updated [1]. V grade and B grade devices differ only in test flow, the construction and on-package chip capacitors are identical.


[1] https://www.xilinx.com/support/documentation/data_sheets/ds192_V5QV_Device_Overview.pdf
